Samsung Electronics Set to Unveil 'zHBM' Stacked on GPU, Targeting AI Bottleneck Breakthrough

Samsung Electronics is set to unveil its next-generation 3D memory and storage roadmap designed to resolve performance bottlenecks in AI (artificial intelligence) systems. The centerpiece is 'zHBM' technology, which vertically stacks HBM (High Bandwidth Memory) directly on top of GPUs. SK Hynix is also entering the next-generation AI memory semiconductor race in earnest with its tiered memory system.

According to industry sources on the 3rd, Samsung Electronics will showcase a broad range of 3D memory and storage technologies optimized for AI workloads at the 'FMS (Future of Memory and Storage) 2026' conference, the world's largest memory and storage event, held over three days starting on the 4th (local time) at the Santa Clara Convention Center in California. Lee Jin-yeop, Executive Vice President and Head of Flash Development at Samsung Electronics' Memory Business Unit, and Kim Kyung-ryun, Managing Director of the DRAM Development Office in the Memory Business Unit, will deliver keynote addresses. This year's FMS marks the event's 20th anniversary and is regarded as the largest gathering in the memory and storage industry.

A Samsung Electronics representative stated, "At FMS 2026, we will redefine AI systems through 3D memory and storage innovation," adding, "We plan to introduce next-generation HBM and V-NAND (vertical stacked NAND flash) technologies optimized for AI workloads." Notably, industry observers widely expect the 'zHBM' — a next-generation HBM applying 3D stacking technology — to be unveiled for the first time at this event.

zHBM represents an entirely new memory architecture that stacks HBM vertically on top of GPUs (Graphics Processing Units). First revealed by Samsung Electronics on February 11 at 'SEMICON Korea 2026,' the technology dramatically shortens data travel distances compared to the conventional side-by-side arrangement of GPU and HBM, simultaneously boosting bandwidth and power efficiency. The difference in data movement paths between the two architectures is illustrated below.

Song Jae-hyuk, CTO (Chief Technology Officer) of Samsung Electronics, emphasized at the time, "zHBM's data transfer speed is four times faster than HBM4 while consuming only one-quarter of the power," adding, "We will achieve another major innovation in bandwidth and power efficiency."

Note: The maximum bandwidth of the HBM4 standard (JESD270-4) officially announced by JEDEC in April 2025 is 2TB/s per stack (based on a transfer rate of 8Gb/s × 2048-bit interface). Applying the '4x' figure cited by CTO Song, zHBM's theoretical bandwidth calculates to approximately 8TB/s per stack.

In the NAND segment, 'z-NAND' is being positioned as the next-generation strategic product. Previously, GPUs had to route through CPUs (Central Processing Units) and DRAM to access data stored on SSDs (Solid State Drives), inevitably introducing latency. z-NAND is a technology focused on minimizing latency and enhancing input/output (I/O) performance to reduce this bottleneck.

At last year's FMS, Samsung Electronics announced it was developing z-NAND with the goal of achieving 15 times the processing performance of conventional NAND while reducing power consumption to one-fifth. Industry observers view the 3D architecture as the next-generation solution to AI system bottlenecks, as reducing inter-chip data travel distances improves bandwidth and power efficiency. The surge in data processing demand driven by the expansion from generative AI to agentic AI and physical AI is also cited as a factor amplifying the importance of 3D architectures.

An industry official explained, "As AI workloads evolve, the volume of data and context requiring processing grows exponentially, making it increasingly clear that conventional compute-centric architectures face limits in improving performance and power efficiency," adding, "3D memory and storage technologies like zHBM and z-NAND represent an attempt to implement memory-centric AI infrastructure by reducing data movement between compute units and memory while simultaneously expanding performance and capacity."

Category	zHBM	z-NAND
Architecture	HBM vertically stacked on GPU	Vertically stacked NAND flash
Key Effect	Minimized data travel distance, improved bandwidth and power efficiency	Minimized latency, enhanced I/O performance
Target Performance	4x transfer speed vs. HBM4, 1/4 power consumption	15x processing performance vs. conventional NAND, 1/5 power consumption

Note: Based on target figures disclosed by Samsung Electronics.

Meanwhile, rival SK Hynix is also countering at FMS 2026 with a tiered memory system built on xPU (processing units), HBF (High Bandwidth Flash), and CXL (Compute Express Link). Kim Cheon-seong, Vice President and Head of the Solution Development Division at SK Hynix, and Kang Uk-seong, Vice President of Next-Generation Product Planning, are scheduled to deliver a keynote on 'Efficient AI Infrastructure Orchestration through Tiered Memory in the Agent AI Era.'

HBF is a next-generation memory being developed by SK Hynix following a joint 'standardization kickoff' event held on February 25 at SanDisk's headquarters in Milpitas, California, where a dedicated workstream was established under the OCP (Open Compute Project). The goal is to create a new storage tier between HBM and SSD, securing both the bandwidth and capacity required for large-scale AI inference services. SK Hynix's recently unveiled tiered architecture 'IMTE (Inference Memory Tiering Expansion)' expands the existing 'HBM→DRAM→SSD' memory hierarchy by adding CXL hybrid memory, resulting in an 'HBM→DRAM→CXL memory→SSD' structure. In this design, CXL memory predicts which data HBM and DRAM will need and prefetches it from SSDs. Taiwan-based market research firm TrendForce, citing a Seoul Economic Daily report, stated this architecture improves AI inference efficiency by 35.7% compared to conventional designs.

The next-generation memory and storage technologies unveiled by the two companies around FMS 2026 are summarized below.

Company	Technology	Core Concept	Announcement Timing	Target/Effect
Samsung Electronics	zHBM	HBM vertically stacked on GPU via TSV	First revealed 2026.2.11 at SEMICON Korea	4x transfer speed vs. HBM4, 1/4 power consumption
Samsung Electronics	z-NAND	Vertically stacked NAND flash	Development targets announced at FMS 2025	15x processing performance vs. conventional NAND, 1/5 power consumption
SK Hynix	HBF	New storage tier between HBM and SSD	2026.2.25 OCP standardization initiated with SanDisk	High-capacity, high-bandwidth memory for AI inference
SK Hynix	IMTE	CXL hybrid memory connecting HBM/DRAM with SSD	2026.7 TrendForce report (citing Seoul Economic Daily)	35.7% improvement in AI inference efficiency vs. conventional

Note: zHBM and z-NAND figures are Samsung Electronics' disclosed targets; HBF and IMTE are based on the joint SK Hynix-SanDisk announcement and TrendForce report, respectively.

This event is expected to demonstrate that competition in the AI semiconductor market is shifting from simple performance battles to 'system architecture' innovation. As data movement bottlenecks between GPUs and memory emerge as the critical variable determining overall AI system performance, the technological capabilities of memory semiconductor companies have become a decisive factor in the success of AI infrastructure. All eyes are on how the 3D memory technologies from Samsung Electronics and SK Hynix will reshape the competitive landscape of the AI semiconductor market.