Shanghai Startup Dongfang Suanxin Bets on 14nm, 3D Stacking to Sidestep US Chip Curbs

A two-year-old Shanghai semiconductor startup valued at over $1.7 billion has officially ended its stealth mode, unveiling a new AI chip architecture designed to challenge NVIDIA's dominance without relying on the most advanced manufacturing processes or high-bandwidth memory (HBM) restricted by U.S. export controls.

Dongfang Suanxin introduced its flagship DF1000 processor at a launch event on Monday, ahead of the World Artificial Intelligence Conference (WAIC) 2026. The chip is fabricated on a mature 14-nanometer process, yet the company claims it delivers 520 teraflops of BF16 computing performance—a standard metric for large-scale AI model training—and 6.4 TB/s of memory bandwidth.

The startup's strategy revolves around two architectural pillars: a software-defined computing framework and 3D-stacked near-memory computing. Instead of engaging in a brute-force race for smaller transistors, Dongfang Suanxin aims to reconfigure how chips process and move data, effectively bypassing the physical limitations imposed by sanctions on cutting-edge chipmaking equipment.

"We have to forge a path of our own," founder Wei Shaojun said during the launch. "That path cannot be about passively catching up within a framework set by others. We need independent architecture, original technology, a self-sustaining ecosystem and a secure, controllable supply chain."

Wei, a prominent figure in China's semiconductor landscape who previously served as a Tsinghua University professor and vice chairman of the China Semiconductor Industry Association, has attracted a heavyweight roster of backers. According to the 《Securities Times》, the company reached a valuation of RMB 12.3 billion following a Series A+ funding round in April 2026. Investors include the National AI Industry Investment Fund, Zhangjiang Hi-Tech Park, Hillhouse Capital, and venture arms linked to Meituan (3690.HK), Xiaomi (1810.HK), JD.com (JD), and Didi.

The DF1000: Breaking the Memory Wall

On paper, 520 TFLOPS of BF16 performance does not dramatically outpace existing high-end processors. The DF1000 delivers approximately 52.6% of the per-chip computing performance of NVIDIA's Hopper-based 4nm H100/H200, according to industry blog ICSmart.

Where the chip stands out is its memory bandwidth. At 6.4 TB/s, the DF1000 offers nearly twice the bandwidth of NVIDIA's H100 and roughly 33% more than the H200. In large language model training and inference, the bottleneck is often not raw calculation speed but the time and energy spent shuttling data between memory and processing cores—a problem known as the "memory wall."

The startup tackles this by using hybrid bonding to vertically stack the logic layer and DRAM layer, shrinking interconnect pitches from tens of microns down to the sub-micron level. While the memory does not directly perform computation, its proximity to the logic dies slashes data travel distances, reducing latency and power consumption. This 3D-stacked near-memory architecture allows conventional DRAM to replace HBM, a critical advantage given that advanced HBM is subject to U.S. export controls.

"Amid restricted access to advanced processes, the company has adopted software-defined chips combined with 3D-stacked near-memory computing," Wei explained, as reported by 《Jiemian News》. The report added that the entire DF1000 supply chain is domestically sourced.

The DF1000 accelerator card follows the OAM 2.0 specification, making it compatible with mainstream AI servers from domestic original equipment manufacturers (OEMs) and supporting both air and liquid cooling. The company also showcased a 128-card cluster built around the DF1000, with a liquid-cooled server housing eight cards connected via Full Mesh topology, achieving 900 GB/s of scale-up bandwidth per card.

Software-Defined Flexibility

Beyond the silicon, Dongfang Suanxin is betting on a "software-defined" approach to differentiate itself. The chip uses a reconfigurable computing array and dataflow architecture, allowing it to reorganize its computational pathways based on the specific model, operator, and precision required. The goal is to strike a balance between the generality of GPUs and the high efficiency of application-specific integrated circuits (ASICs).

This flexibility is increasingly critical as Chinese AI models like DeepSeek, GLM, and Qwen evolve rapidly. A rigid chip design risks obsolescence with each new model architecture, but pure general-purpose chips struggle to compete on energy efficiency.

To support developers, the company launched the CAAP software stack, which supports mainstream development frameworks alongside custom programming for operators, supernodes, and computing clusters. The software ecosystem remains the hardest nut to crack for domestic AI chipmakers, whose historical pain points have included painful model migrations, operator adaptation, framework compatibility, and cluster stability—not just peak parameter counts.

An Ambitious Roadmap

Dongfang Suanxin is not stopping at one chip. The company outlined an aggressive roadmap targeting NVIDIA's most advanced offerings:

Product	Expected Launch	Target Competitor	Key Claim
DF2000	Q4 2026	NVIDIA H200 (4nm)	Twice the performance of DF1000
DF3000	Late 2027	NVIDIA B300	Double DF2000 performance

Despite the bold timeline, Wei acknowledged the inherent challenges. According to the 《South China Morning Post》, he noted that stacking multiple silicon layers often lowers manufacturing yields. More fundamentally, limited domestic access to advanced fabrication nodes remains the ultimate performance ceiling for China's semiconductor industry.

"3D stacking alone has its limitations," Wei cautioned. The admission underscores the reality that architectural innovation, while promising, cannot fully compensate for a multi-generational gap in process technology.

A Broader Industry Shift

Dongfang Suanxin's debut reflects a broader strategic pivot among Chinese chip firms. With access to cutting-edge lithography tools and advanced nodes blocked, companies are increasingly exploring software optimization, novel memory hierarchies, and advanced packaging to squeeze more performance from mature manufacturing processes.

The startup's pitch to the market is essentially a new playbook for domestic high-end computing: use a mature 14nm process for fabrication, break through the bandwidth, memory, and power walls with software-defined 3D near-memory architecture, and deliver complete systems at the server and cluster level.

The DF1000 is ready for mass production, with first shipments expected before the end of 2026. But 520 TFLOPS and 6.4 TB/s remain specification-sheet figures. The real test will be whether the chip's model-level performance, software maturity, cluster scaling efficiency, and customer deployments can justify the hype surrounding this billion-dollar unicorn.